The present invention relates generally to microprocessors, and more particularly to an architecture of a microprocessor that is particularly well adapted for controlling cellular radiotelephone transceivers.
As radiotelephone systems increase in size and complexity to accommodate greater numbers of mobile and portable radiotelephones operating in geographic areas including several large cities or even several states, it is necessary that the control circuitry of these radiotelephones becomes increasingly sophisticated. For example, in cellular radiotelephone systems, mobile and portable radiotelephones must be capable of transmitting and receiving high speed, supervisory signals on dedicated signalling radio channels and also on voice radio channels during conversations. Prior radiotelephone control circuitry, such as that described in U.S. Pat. Nos. 3,458,664 and 3,571,519, does not have the capacity for processing these high speed, supervisory signals required to be received and transmitted during normal operation in such cellular radiotelephone systems. Conventional microprocessors have been integrated into some prior radiotelephones, such as the radiotelephone in U.S. Pat. No. 4,122,304, for providing additional telephone type features, such as automatic telephone number dialing, to radiotelephone subscribers in the present day improved mobile telephone system (IMTS) provided and operated by many telephone companies. However, conventional microprocessors lack the capacity to accommodate the high speed, supervisory signalling encountered in cellular radiotelephone systems, while at the same time monitoring and controlling other portions of the radiotelephone, such as the transmitting and receiving circuitry, a keyboard, and a telephone number display. Moreover, conventional microprocessors having high speed processing capability consume excessive amounts of power, rendering them impractical for use in battery operated mobile and portable radiotelephones.